DSP System Design through VHDL in the Ptolemy Environment

In Ptolemy, we have produced a working VHDL target for code generation, which allows for structurally oriented VHDL code generation of systems which combine existing VHDL library entities. This effort provides a basic infrastructure for generating top-level VHDL design specifications. The target has been expanded to allow fully hierarchical designs to be output into complete VHDL specifications. These designs are composed of predefined VHDL blocks connected according to the block specifications, and then elaborated to a full design by the code generator.

There are two distinct VHDL domains which follow this structure. They are VHDL-Functional (VHDLF) and VHDL-Behavioral (VHDLB). The functional domain is intended for the design and simulation of algorithms solely to check their functional correctness. The behavioral domain, in contrast, can be used to represent functionality plus timing details, including time-dependent behavior of components, propagation delay through components, clocking constraints, and scheduling demands.

The motivation for splitting between functional and behavioral domains is to improve the design process both for the user and for the tools which may act upon the resulting output of the VHDL domains. From the user's perspective, the split parallels the conceptual distinction between abstract system design and concrete implementation design. By deferring timing issues until the behavioral domain, we also avoid overspecifying the system early in the design process, concentrating first on the functional behavior of the system. Finally, this distinction allows for a clean separation of design styles, which is more natural to the ways in which designers think about systems at the algorithmic level as opposed to the implementation level. The VHDL language is highly expressive and is capable at both levels, but it unnecessarily complicates the design process to require users to work at multiple levels simultaneously.

From the perspective of using high-level synthesis tools, keeping the functional and behavioral design styles distinct allows for generating VHDL code that is geared toward the target tool. Such tools may be able to optimize their output depending on whether or not the input specification is a dataflow description or some other style of representation. By using Ptolemy's retargeting capability, a single design specification in Ptolemy can be used to generate multiple styles of VHDL code, such as structural, sequential statements, or concurrent processes. Different target tools will find one or more of these styles more suitable to their aims, and allowing for such retargeting can improve the overall results of the design process.

Future work will include improvements to the Ptolemy/VHDL co-simulation environment we have constructed, including improvements to the range of targeting options available. Further work will allow an easier migration from dataflow simulation domains to the VHDL domains.