1996 Research Summaries for the Ptolemy Project

Control Logic Generation for Performance Estimation of High-Performance Pipelines


Researcher:Yoshio Miki
Advisor:Edward A. Lee
Sponsors:Hitachi Ltd. and the Ptolemy Project

Design exploration at the system-level plays an important role in multi-media or telecommunication systems. At this level, designers typically estimate chip area and system delay while they are composing system functions. Estimation methods [1][2] provide area and delay estimates, given functional blocks in the design. However, the performance requirements often also require optimization in more low-level details. In particular, control logic becomes a more important part of the design.

This project is focusing on a control logic generation for a pipelined design. It uses the SDF (synchronous dataflow) and DE (discrete event) domains in Ptolemy to develop a high-level design methodology for high-performance systems. To reduce the cycle time between architecture design in SDF and estimation in DE, our algorithm generates control logic in the DE domain that avoids resource and data hazards. Designers can concentrate on system-level issues in the SDF domain.

The algorithm begins by generating transfer logic corresponding to each pipeline stage. Next, it generates supervisory controls that avoid hazards. This style of behavior-level logic synthesis has been shown to be implementable as sequential logic [4]. In our procedure, hazards are detected using a trace procedure on a data flow graph. Control logic for data hazards is generated as arbitration logic in adjacent functional blocks. This means the resource hazards can be detected from the static topological relations of the data flow graph. To detect data hazards, our algorithm checks all blocks in a directed loop.

A prototype implementation uses the scripting interface to Ptolemy (ptcl), translating system specifications from one form to another. We are planning to extend scripting language itself to enable a higher level interface.

  1. J.M. Rabaey, C. Chu, P. Hoang and M. Potkonjak, "Fast Prototyping of Datapath-Intensive Architectures", IEEE Design & Test of Computers, pp.40-51,1991
  2. S. Bakshi and D.D. Gajski, "Design Exploration for High-Performance Pipelines", ICCAD 94', pp.312-316, 1994
  3. J. Buck, S. Ha, E.A. Lee and D.G. Messerschmitt, "Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems", Int. J. Computer Simulation, Vol.4, pp.155-182, 1994
  4. P. Schaumont, B. Vanthournout, I. Bolsens and H.D. Man, "Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling", Int. Sympo. on System Synthesis, pp.72-77, 1995

Send comments to Yoshio Miki at ymiki@eecs.berkeley.edu.