Automatic Code Generation for Heterogeneous Multiprocessors

Target Specification

A key property of Ptolemy that makes specification of heterogeneous targets easier is its use of object-oriented programming techniques. In describing a multiprocessor target, we begin with the specification of each individual processor and build multiprocessor targets hierarchically from these objects. A target specification in Ptolemy manages the flow of the design process; i.e., it defines the methods to schedule the graph, compile and run the generated code, taking into account the target resources. A detailed description of the code generation framework in Ptolemy can be found in [9] and with emphasis on single processor targets in [10].

The fundamental building block of a multiprocessor target is a single processor target. In our example, we have multiple Ariel S-56X cards installed in a workstation. An S56X target describes one of the DSP cards. This target knows the exact memory resources available on the card and how download the code into the program memory of the DSP. The S56X target generates assembly code and allocates target-specific resources such as private memory. A CGC target describes the resources of the workstation and generates code in the C programming language. This target is a more general type of target than the S56X target. The code it generates can run on most general-purpose computers.

A multiprocessor target is built from other targets that it contains as children in a hierarchy. These children can be any type of target, from a simple single processor to a complex heterogeneous multiprocessor. The parent multiprocessor target specifies the shared resources and IPC mechanisms of the children. A homogeneous multi-DSP target description is detailed in [11].

The CGC-S56X heterogeneous target is a multiprocessor target containing multiple S56X target children together with a CGC target. The S56X target was used to implement a real-time ADPCM speech coder described in [10]. Simpler examples are provided below to illustrate key features of the different interfaces.

Automatic Code Generation for Heterogeneous Multiprocessors

[Next] [Previous] [Top]