Processor/Compiler Co-Design of DSP and Embedded Systems:
A Quantitative Approach
Vojin Zivojnovic
Institute for Integrated Systems in Signal Processing (ISS)
Aachen University of Technology.
Thursday, April 3rd, 1997
Hogan Room, 531 Cory Hall
5:00-6:00 p.m.
Abstract:
The newest introduction of highly complex architectures, like the
TMS320C6xx, redefined definitely the role of compilers in the software
design methodology for DSP and embedded systems. From the productivity
problem, DSP compilation evolved to the feasibility problem of complex
software designs. The DSP compilation field activity faces currently an
increasing interest of the industry and academia. The talk provides an
overview of the QUANT design environment for joint processor/compiler
design developed at the Aachen University of Technology. The three main
components of the QUANT environment are discussed --- benchmarking
methodology DSPstone, fast processor simulation technique SuperSim, and
machine description language LISA. The first part of the talk
concludes with the summary of main results of the QUANT project and
their impact on the industry and academia since introduction in 1993.
In the second part, the newest results on the bit- and cycle-accurate
compiled ISA simulation of the TMS320C54x processor are presented. The
new simulator delivers a simulation speedup between 25 and 170 times
compared to the existing commercial solution. The high speed enables an
efficient exploration of the processor/compiler co-design space, and
the analysis of the interplay between various compiler optimizations.
The applied trace simulation technique is presented and the sources of
the speedup, as well as the directions for further work are discussed.
Biography:
Vojin Zivojnovic is a senior researcher at the Institute for
Integrated Systems in Signal Processing (ISS) of the Aachen University
of Technology. Prior to joining ISS in 1992 he was with the Institute
for Nuclear Sciences - Vinca and with the Electrical Engineering
Faculty of the University of Belgrade, Yugoslavia. His research
interests are in the design automation of DSP systems, graph-theoretic
models of signal processing algorithms and higher-order statistical
signal processing. He received the B.Sc. and M.S. degrees from the
University of Belgrade, Yugoslavia in 1983 and 1986, respectively.