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Managing Complexity in Heterogeneous System Specification, Simulation, and Synthesis

1 Introduction

Typical applications of embedded systems include telecommunications, consumer products, robotics, and automotive control systems. Such embedded systems exhibit heterogeneity in implementation (hardware/software) as well as computational semantics (control/dataflow). As a result of increasing functional complexity, these systems are usually designed in a top-down manner, starting with a behavioral specification. The design of such heterogeneous hardware/software systems is often referred to as hardware/software codesign or system-level design. In this context, the key design problems are hardware/software partitioning, cosynthesis, and cosimulation [1].

A typical design flow

for the hardware/software codesign problem [2] is shown in Figure 1. A behavioral-level design specification (ex: modem.sdf) is transformed into the final implementation, consisting of custom and commodity programmable hardware components and the software running on the programmable components, by passing through a sequence of tools. This is not a black-box push-button design process, but involves considerable user interaction. The user experiments with different design choices; design space exploration is the key to system level design. Managing the complexity of this design process is non-trivial. The features needed for efficient design space exploration include:

For example, in Figure 1, the user might be interested in first determining if a feasible partition exists. At this point only the Estimation and Partition tools need to be invoked; subsequent tools need not be run. Inefficiencies due to unnecessary tool invocations can be avoided if flows are specified modularly as in Figure 1.
A number of design options are available at each step in the design process. For instance, the Partition tool can be one of: a human-intervened manual partitioning, an exact but time consuming tool such as CPLEX using integer linear programming techniques, or an efficient custom optimized algorithm such as GCLP [3]. Depending on the available design time and desired accuracy, one of these is selected. This selection can be done either by the user, or by embedding this design choice within the flow. A design flow with a configurable methodology is thus easily extensible.

After developing a particular design, the user might want to experiment with other options, for instance, different hardware synthesis mechanisms. One possible approach to hardware synthesis is Silage code generation followed by Hyper [4]. An alternative path is VHDL code generation followed by Synopsys tools [5]. If a specific tool is changed on the fly, the entire system need not be re-run; only those tools that are affected should be run (in this case: Hardware Synthesis, Netlist Generation, Simulation).

Detecting incompatibilities between tools and maintaining versions of the tools and design flows is necessary.

In this paper we propose an infrastructure that manages these aspects of the system-level design methodology. The end goal is to use this infrastructure to build a codesign system. Section 2 briefly mentions mechanisms for specification, simulation, and synthesis of heterogeneous designs. Section 3 presents the underlying concepts of design methodology management. Section 4 discusses implementation details and gives an example design flow that demonstrates the viability of our approach.

Managing Complexity in Heterogeneous System Specification, Simulation, and Synthesis

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