Joachim Kunkel
Advanced Technology Group
Synopsis Inc.
October 17, 1996
Hogan Room, 531 Cory Hall
4:00-5:00 p.m.
The ability to put 100 million transistors on a single chip in the near future poses new challenges both at the front end as well as the back end of the design process. While the problems at the back-end are well understood and tools are being developed to address the new challenges, the situation looks different at the front end of the design process. In spite of the fact that there seems to be some sort of general agreement that higher levels of abstraction combined with a reuse based design methodology will provide the additional productivity required to handle the complexity of these designs, little has been said about how exactly this translates to new design methodologies and design tool capabilities.
This talk first examines the current capabilities of High Level Design (HLD) and Electronic System Design Automation (ESDA) Tools and their applicability to the design of "Systems on Chip". It then ventures into speculation about the future role of design tools for these highly complex systems.