High-Performance DSP System Design Approaches

Keshab K. Parhi
Dept. of Electrical and Computer Eng.
University of Minnesota, Minneapolis

Friday, September 19th, 1997
Hogan Room, 531 Cory Hall
4:00-5:00 p.m.

Combined DSP/Systems Modeling seminar


This talk will address approaches to high-performance DSP system implementations. First part of the talk will be directed towards design methodologies for implementation of low-area and/or high-speed DSP systems. Second part of the talk will be directed towards design of low-power DSP systems.

Several systematic transformations for synthesis of low-area and high-speed DSP systems are presented. First implementation of parallel FIR filters using strength reduction approaches is presented. This is based on use of efficient low-complexity small-length parallel FIR filters. There exist many possible parallel FIR filter toologies of same complexity. It is shown that selection of appropriate topology based on the filter frequency characteristics is important for further reduction of number of adders in the parallel filters. Next we present pipelining of recursive least square (RLS) adaptive filters. Two approaches to this end are presented. First, we present a novel technique referred to as matrix-look-ahead to pipeline the Given's rotation based RLS adaptive filters. The complexity in terms of the number of rotations in this approach increases linearly with respect to level of pipelining. Second, we present a novel alternate rotation (referred to as Scaled TAngent Rotation or STAR) to pipeline RLS adaptive filters with significantly less complexity. Finally we present systematic transformation approaches for multi-rate and multi-dimensional retiming and folding. These approaches are exploited for systematic implementation of folded one-dimensional wavelets, two-dimensional IIR filters and two-dimensional wavelets. In this context memory minimization is also addressed.

The second part will address design of low-power computation-intensive DSP systems. First a tool referred to as HEAT (Hierarchical Energy Analysis Tool) will be presented. This tool can estimate power consumption in two-orders of magnitude less time with 5-8% error as compared with Spice. Then novel implementation of low-power adders will be presented. A novel cell-replacement transfomation is used to design various digit-serial multipliers. It is shown that these can be operated with 15 times less power than non-pipelined bit-parallel multipliers at same speed. Finally approaches to finite field multiplication are presented and design of a data-path for programmable low-power Reed-Solomon codec is presented.