Automatic Code Generation for Heterogeneous Multiprocessors

Basic Interface

When a dataflow graph is partitioned by an SDF multiprocessor scheduler, pairs of send and receive actors are automatically spliced into the graph wherever IPC occurs. Hence, the location of the splicing is typically determined by the scheduler and not the user. For multiprocessor targets, scheduling is performed at the top level; the children are provided with the resultant schedule for their processor(s). Any user-specified hierarchy is ignored in order to fully exploit the parallelism that exists in the graph.

However, there are disadvantages with using one of the presently available SDF parallel schedulers. In many practical situations, such as with heterogeneous targets, the user knows a reasonable actor partitioning over the processors. Parallel schedulers are hard to implement and do not perform many of the optimizations that are available with uniprocessor schedulers, such as code compaction[6] and buffer minimization[12]. Furthermore, schedulers such as BDF do not support multiprocessor platforms, but are very attractive to express data-dependent control flow with low run-time overhead.

Automatic Code Generation for Heterogeneous Multiprocessors

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