Automatic Code Generation for Heterogeneous Multiprocessors
For this interface we restrict the outside system to be a simulation. To construct the code generation side, we splice in CGC actors that are designed to communicate directly to the EventHorizon. If the inside target is CGC, the interface is fully specified. However, if it is not CGC, a CGWormhole is constructed between CGC and the intended target, as detailed in the previous section. Finally, the C code for this interface is dynamically linked into the Ptolemy binary.
As an example, we use the CG-Sim-Wormhole as a simple test/monitoring system for the DSP card. This example demonstrates multiple streams of data flowing between the workstation and DSP at different rates.
Figure 4 shows the hierarchical graph detailing the example. The S56XIO block, which appears expanded above the main graph, is executed on the DSP card installed in the workstation. All other blocks run in a Ptolemy SDF simulation. Externally, the S56XIO block appears to be an SDF simulation block; however, before the simulation is run, code is automatically generated and downloaded to the DSP card.
When data reaches the input of the S56XIO block, it is downloaded to the DSP card. Here it is forked; on one branch it is downsampled by a ratio of 2:1 and on the other it is multiplied by a gain of 0.5. The results are then uploaded to the workstation for display using XGraph blocks.
A primary motivation for the construction of this interface is to embed an actual hardware implementation of an algorithm into a high-level simulation. Other uses of this CG-Sim-Wormhole include hardware acceleration, algorithm development/migration and debugging. This work is similar to the hardware and simulation interface presented in [13]. The major distinction is that this interface is one of a trio of interfaces all built automatically from the same send and receive actors.