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Automatic Code Generation for Heterogeneous Multiprocessors

References


[1] J. Buck, S. Ha, E.A. Lee, and D.G. Messerschmitt, "Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems," International Journal of Computer Simulation, special issue on Simulation Software Development, to appear 1994.

[2] E.A. Lee and S. Ha, "Scheduling strategies for multiprocessor real-time DSP.," GLOBECOM '89, 1989, p. 1279-83 vol.2.

[3] D.G. Powell, E. A.Lee, and W.C. Newman, "Direct Synthesis of Optimized DSP Assembly Code from Signal Flow Block Diagrams," ICASSP, vol. 5, San Francisco, CA, IEEE, 1992, p. 553-556.

[4] S. Ritz, M. Pankert, and H. Meyr, "High level software synthesis for signal processing systems," Proceedings of the International Conference on Application Specific Array Processors, Berkeley, CA, USA, IEEE Comput. Soc. Press, 1992, p. 679-693.

[5] E.A. Lee and D.G. Messerschmitt, "Synchronous data flow," Proceedings of the IEEE, vol. 75, no. 9, 1987, p. 1235-1245.

[6] S.S. Bhattacharyya, Scheduling synchronous dataflow graphs for efficient iteration, Master's Thesis, University of California at Berkeley, 1991.

[7] G.C. Sih and E.A. Lee, "Declustering: A New Multiprocessor Scheduling Technique," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 6, 1993, p. 625-637.

[8] J.T. Buck and E.A. Lee, "Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model," ICASSP, Minneapolis, IEEE, 1993.

[9] J.L. Pino, S. Ha, E.A. Lee, and J.T. Buck, "Software Synthesis for DSP Using Ptolemy," Journal of VLSI Signal Processing, Synthesis for DSP, 1993, to appear.

[10] J.L. Pino, Software Synthesis for Single-Processor DSP Systems Using Ptolemy, Master's Thesis Memorandum UCB/ERL M93/35, University of California at Berkeley, 1993.

[11] S. Sriram and E.A. Lee, "Design and Implementation of an Ordered Memory Access Architecture," ICASSP, Minneapolis, MN, IEEE, 1993.

[12] P.K. Murthy, S.S. Bhattacharyya, and E.A. Lee, "Minimizing Memory Requirements for Chain-Structured Synchronous Dataflow Programs," ICASSP, Adelaide, South Australia, 1994.

[13] M. Pankert, S. Ritz, and H. Meyr, "Integration of digital signal processing hardware into a system level simulation environment," Proceedings of the European Simulation Multiconference, York, U.K., 1992, p. 147-151.

This work was supported by grants from NSF (MIP 9201605), AT&T, ONR, and SRC (grant number 92-DC-008).


Automatic Code Generation for Heterogeneous Multiprocessors

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