1996 Research Summaries for the Ptolemy Project

A Hierarchical Algorithm Specification and Test Environment for Video Signal Processing Architectures

Researcher:Farhana Sheikh
Advisor:Edward A. Lee
Sponsors:Canadian NSERC 1967 Scholarship and the Ptolemy Project
Over the past decade, the communications industry has seen a dramatic increase in the demand for applications that require high quality video. This has come about mainly because of major advances in the multimedia industry, making it possible for many consumer electronic services and products to incorporate video. Such applications include high definition television, medical imaging systems, and teleconferencing systems. The design of such systems invariably includes the incorporation of complex video processing algorithms which must process large amounts of data in real-time. These constraints make software implementation of such algorithms infeasible, yet non-programmable hardware is not conducive to modifications of the algorithm.

The need for flexible and programmable hardware for real-time execution of video algorithms has resulted in the development of programmable digital video signal processors. These architectures are characterized by their very long instruction word (VLIW) architecture and the ability to incorporate fine-grained parallelism to achieve high computing power and high communication bandwidth.

The advent of these specialized architectures has in turn resulted in a need to provide design engineers with a development environment that will enable the engineer to easily specify the algorithm to suit the underlying hardware architecture and to be able to see the results of the implementation in real-time. The existence of such an environment can greatly reduce the time to successfully implement the algorithm in a consumer product and its time to market.

The goal of this project is to design and incorporate a hierarchical algorithm specification and test environment into Ptolemy to support rapid prototyping and real-time simulation of new video processing algorithms. The intention is to support a formal graphical specification of the video algorithm, automatic code generation, and scheduling of the algorithm onto the video signal processor (VSP). Some of the major requirements of the project are to provide the design engineer with an environment that is simple to use, allows interactive control over algorithm parameters, and allows the design engineer to observe the visual effects of the algorithm by executing it in real-time. The project aims to simplify for the design engineer all stages of algorithm development process, from conception to the testing phase.

Send comments to Farhana Sheikh at farhana@eecs.berkeley.edu.